Monday, January 31, 2011

What have SONY put into their new handheld?

ARM Cortex 9
For the next generation PSP - PSP2 or NGP - Sony has abandoned the internally developed MIPS architecture that powered the PSP, and has opted for an ARM processor, with a PowerVR graphics processing unit. This puts the machine inline with massive majority of high-end smartphones: ARM reckons 95% of all current mobile handsets have application processors based on its IP, while Imagination Technologies, the developer of the PowerVR graphics chipset, claims 200 current models feature its technology. ARM and PowerVR chips are in the Apple iPad as well as high profile Google handsets such as the Galaxy S.

Cortex-A9 Processor

The ARM Cortex™-A9 processor provides unprecedented levels of performance and power efficiency making it an ideal solution for designs requiring high performance in low power or thermally constrained cost-sensitive devices.

Available as either a single core or configurable multicore processor, with both synthesizable or hard-macro implementations available. This processor can scale across a wide variety of applications while enabling a consistent software investment across multiple markets.

The Cortex-A9 processors are the highest performance ARM processors implementing the full richness of the widely supported ARMv7 architecture. Designed around the most advanced, high efficiency, dynamic length, multi-issue superscalar, out-of-order, speculating 8-stage pipeline, the Cortex-A9 processors deliver unprecedented levels of performance and power efficiency with the functionality required for leading edge products across the broad range of consumer, networking, enterprise and mobile applications.

The Cortex-A9 microarchitecture is delivered within either a scalable multicore processor, the Cortex-A9 MPCore™ multicore processor, or as a more traditional processor, the Cortex-A9 single core processor. Supporting the configuration of 16, 32 or 64KB four way associative L1 caches, with up to 8MB of L2 cache through the optional L2 cache controller, the scalable multicore processor and the single processor provide the broadest flexibility and are each suited to specific applications and markets.

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